Research Journal of Recent Sciences _________________________________________________ ISSN 2277-2502 Vol. 3(6), 96-104, June (2014) Res.J.Recent Sci. International Science Congress Association 96 Review Paper An Overview of through-Silicon via – based Three Dimensional integrated Circuits (3D IC) to placement to Optimize timingMohammad Trik, Behzad Boukani, Babak Ansari,Siavash Emtiyaz, Shilan Rahmani Azar and Fardin Mohammadi Darvandi Young Research Club, Sardasht Branch, Sardasht Islamic Azad University, Sardasht, IRANAvailable online at: www.isca.in , www.isca.me Received 21st May 2013, revised 18th October 2013, accepted 10th December 2013Abstract Semiconductor technology continues its progress in the field of 3DICs. Using stack structures through silicon via (TSV), the concept of 3D IC deals with introducing another dimension in recent designs. In fact, 3D ICs accompanying with TSV cells replace the existent connections in 2D ICs. Optimizing 3D ICs; however, is still in its early stages in many aspects. There are still some problems in locating standard and TSV cells regarding time optimization. In the present study, after queuing the layer and based on its segmentation, first we proposed a methodology for locating cells. Then, we dealt with simultaneous addressing of the pressure caused by the queuing process. Simulated fusion was applied to optimize timing and reduce wire length. Finally, an appropriate method is used to prove the procedures so that it can omit the overlaps between the cells and also the TSV cells. The results of the conducted experiments showed that both wavelength and delay in critical routes are more important in 3D ICs compared to 2D ICs. Keywords: Through-silicon, 3D IC, optimize timing,TSV. Introduction Stack multilayer ICs which are usually known as 3D integrated circuits have drawn scholars’ attention in recent years. The main reason for this is that 3D ICs provide more compaction density which in turn causes the performances of timing, wire length, and power to remarkably enhance. Many scholars have recently tried to develop 3D ICs. There are several major reasons for developing the technology of 3D ICs. First, one of the characteristics of 3D technology is that regarding the wire length it provides a better performance compared to 2D ICs and is considered as a substantial solution in industry after applying Moor Law. By introducing TSV, signals can connect cells possessing different layers and wire length can significantly drop. This can be gained through preventing heavy traffic in the surface. The second reason reasons for developing the technology of 3D ICs is that moving standard and TSV cells in 3D integral circuits is crucial. Although an enormous body of research has been conducted on the issue, 2D moving technology has not reached its evolution stage1 (figure 1). Traditional procedures of designing 2D integral circuits should be modified in order to achieve the best advantages of 3D ICs. In other words, moving algorithms in 2D ICs should be structurally examined and modified before they are used in 3D ICs. Performance-based algorithms of movement divide similar indices in order to promote the algorithms. Examine simultaneous timing of wire length. The final goal of 3D ICs is to minimize the wire length in crucial routes so that timing compression can be heightened Timing algorithms on 2D ICs can be classified into two groups named “route-based” and “network-based” algorithms. In route-based approach, delays in crucial route are directly managed. However, direct change of routes and their optimization are rather impractical because there are a lot of crucial routes. As opposed to this approach, network-based approach is simpler and also has less complexity compared to the route-based approach. Figure-1 Internal Connections in 2D and 3D Integral Circuits Research Journal of Recent Sciences ______________________________________________________________ ISSN 2277-2502Vol. 3(6), 96-104, June (2014) Res. J. Recent Sci. International Science Congress Association 97 In route-based approach, timing information is converted into forms of cost amounts. Afterwards, crucial routes along with higher weights can be devoted to the crucial routes timing progress. In network-based approach, special pressures emerge and optimization is applied in order to minimize the amount of a special goal. The amount of the goal generally consists of minimizing crucial route delay or problems. However, timing should acceptably be reduced. Timing has been one of the main concerns in designing 2D integral circuits and this concern has peaked in designing 3D ICs. Standards and requirements are more important in 3D ICs compared to their similar counterparts. In this regard, timing and industrializing them require more attention. In the present study, we have proposed a timed movement based on locating design for 3D ICS.The rest of the article is organized as follows. In section 2, we introduce movement-based classification, timing model, and problem of timed movement in 3D ICs. Section 3 presents an explanation of timed movement methodology in 3D ICs. Section 4 includes the experimental results. Afterwards, results and suggestions for further research are presented in 5 sections. PreliminariesClassification-based Movement: Classification-based movement is generally related to algorithm-based movement. Algorithms of classified movements are multilayer graphs that have a very high performance pace; therefore, they are more appropriate in large scales. Timing problem can be considered in locating the wire by adding extra timing cost in the classified algorithm. By searching the cut lines, classification-based movement is involved with dividing Mira environment into independent sections. Similarly, the overall design is divided into a lot of sub-circuits. Every sub-circuit, in turn, is assigned to an independent section. This process repeats as many times as the amount of the goal or the number of the cuts minimize. In our performance stage, we finish the process so that the size of the sub-circuits reduces as the smallest section as possible. In designing standard cells, classification continues as far as the size of locating area becomes equal to the row height and during verification stage the cells can locate in the rows. Generally, movement-based classification is based on Fiduccia Mattheyses’ classification algorithm. This mechanism is based on cell gains. First, primary cell gains are evaluated then cell movement is discussed, which have the greatest gain. After movement of the cells with high gains, updating the list of gains continues as far as the cells move. After the total gains have been assessed, this process finishes. Finally, the utmost total gains are removed and cells that are connected to specials areas are moved. The utmost gain means that there will be the least cut between two groups of separated cells. Process of alternative movement will end when cells with negative gains move, too. Classification-based movement means that the total number of cuts between two sub-circuits and balance areas reduces simultaneously in both areas. Through the conducted experiments, we concluded that groups have connected cells which have a cluster form and cause the performance time to increase and the size of the cut between two sub-circuits to optimize. Timing Model: In order to analyze the timing process, Elmore’s delay model is applied so as to assess connected delay and delay in TSV cells. Implementing TSV and connected delay model is derived from 5 (figure 2). Delay (T) from the beginning to the end can be modeled as follows (1).  (1) Where: is wire resistance, w is the existent capacity, d is the driving output resistance, and is loading capacity of the receivers. This formulation can be replaced by another equation.  \r\r\n (2) Where: is the resistance unit of wire length and is the capacity unit of wire length. Figure-2 Elmore’s Delay Model Designing delay models of TSV is an important aspect in analyzing 3D static timing. Due to having the extra dimension of z, a new delay model can be achieved to assess the timing of z dimension. Here, inducing effect is taken into consideration and the analysis of z dimension timing can be implemented into Elmore’s delay model. The delay of TSV cell is one of the connected delays. Noisiness of TSV cell is explained in Mohammad Aghaei et al6 and Cong J. et al. Resistance of TSV cell (TSV) is a function of conductivity and cross-sectional environment, capacity of a single TSV cell (TSV) and Elmore’s delay form for TSV cells, which is explained as follows (figure 3). Research Journal of Recent Sciences ______________________________________________________________ ISSN 2277-2502Vol. 3(6), 96-104, June (2014) Res. J. Recent Sci. International Science Congress Association 98  \r\r\n (3) Figure-3 TSV Delay Model  (4)   !  \n (5) Where: is TSV length (um), is TSV radius (um), s is sub-layer conductivity, and e is electricity unit of measurement. Formulation of the Problem: Timing problem in 3D ICs can be explained as follows. Considering the graph of G(C, E) which is equal to file definition (def); C and E stand for the cell and the edge, respectively. The number of the moving cells is n. Each cell is ,..., = Î and its coordinate can be defined as. After 3D layers are assigned to them, the cells will distribute on their special layers8,9. A guided edge like ,..., = Î = means that signal direction, constituting cell form of Î is Î . Primary input/output pads cause limitations for the underlying layer that has coordinates with constant characteristics. A number of 3D ICs through m are located in different layers. Each 3D IC makes a connection through,...,TSV = Î . Integral circuit timing introduces two metric units: WNS and TNS. WNS is the worst slack in all final points of timing. Timed points also show the input and output sections of a cell or the first input/output pads of the circuit. TNS is the timed final points which have a negative crack. For every timed point (i), the input time is (arrival). The signal reaches the timed points and the require time means the time that the signal requires at the timed point. The timed crack means that the signals enter and then go into a stage where they need time. All mentioned above can be summarized as follows10: $%&$ ()*+,$%%\n-$.$%&$ %/01234567'\n8 (6) $%&$ ()*+,$%%\n-%9:;%9%/012345'76\n8 (7) Calculation model of wire length in a network is like a closed box in which all network connections can be seen and this can be achieved by calculating half of the perimeter of the primary wire length11. =&#x-230;&#x.718;?@-$.A0+9B'-$.A0+9B'C@-$.A0+95'-$.A0+95' (8) DE@-$.A0+9F'-%A0+9F' (9) Where: e is the network, ci is the cell, and all coordinates are . Our main purpose is to find a systematic locating in TSV cells without any overlaps. At the same time, 3D IC designs can help achieve a better timing performance and reduce wire length, the number of TNS and WNS, and delay on the crucial routes. All over this process, TSV cells continually face balance barriers12,13. Timed Locating Methodology in 3D ICs: Our Methodology Flow: In this section, timed locating algorithm for 3Dclassification which has both sections of time and TSV is presented. The applied methodology is presented in figure 4. This section is organized as follows. First explains classification-based locating and allocation of TSV cellcoordinates14. Next, Elmore’s delay model and analysis of connected delays in TSV cells are presented. In next section, describes timing optimization through Elmore’s delay model and analysis of internal connections and explains systematization process of locating methods. Finally, the method of pressure allocation in TSV locating is explained15,16Classification-based Locating in 3D ICs: The procedure begins with classifying the 2D circuit and converting it into a 3D design. 3D locating area is achieved by dividing the 2D classification area into some layers, which is presented in Figure 5. The width of the cell reduces through multiplying it into the ratio of nl, where: nl is the number of the layers. The area of the cell reduces to nl and the total movement area is equal to 2D scale17,18. Connected mechanism in 3D ICs is achieved through TSV cells and that is why movement of TSV cells affects the total length of the wire and timing performance. The number of TSV cells that require signals in all their layers is specified after each layer has been allocated to a cell. In this stage, TSV cells can cause wire length to decrease. The whole area that occupies the TSV cell is almost wide. Therefore, the overall area and sing TSV cells should be taken into consideration19. Research Journal of Recent Sciences ______________________________________________________________ ISSN 2277-2502Vol. 3(6), 96-104, June (2014) Res. J. Recent Sci. International Science Congress Association 99 Figure-4 Methodology Flow Figure-5 Patterns of 2D and 3D Movements (A stands for area)In order to prevent an increase in TSV cells and keep the overall logical length of the wire in 2D plane, the problem of 3D ICs was simplified through classification-based replacement. Regular and unreasonable performance of the layers from top to the bottom helps standardize the cells through vertical cuts. Each plane can use a two-section method in its row status. In each cycle, cells will be allocated to a specific layer. The process of general locating completes after the alternative classification ends20, 21. The difference between 2D and 3D ICs is that 3D circuits can transmit signals through TSV. In other words, cells in different layers connect to each other through TSV. Different locating of TSV cells leads to different delays. If TSV cells are too far from typical cells, more communication delays may be observed. As opposed to this, if TSV cells are located near special cells where the signals can transmit without any delay, a more favorable condition will be expected22. Coordinate of the cells is specified after classification-based locating. Afterwards, coordinate of the TSV cells can be determined. First, the ratio of average number of TSV cells to the rows is specified. There are a lot of advantages in this method. One of these advantages is that the row has an average distribution for its TSV cells so that it cannot create a huge density for TSV cells. Another advantage is that TSV cells have more opportunities to exchange between different rows23, 24. Coordinate of TSV cells is specified through calculating the center of the box containing the circuits; therefore, TSV cell coordinate is related to the cell coordinate. The main reason for Begin Parser(sdf file & def file & lef file) 3D Partition Total numbers of TSV Static timing analysis Create regions for 3D placement 2D Global plasement TSV cell/land assignment & satisfy Alignment constraint Timing optimization Simulated annealing Localization 3D Plasemen Research Journal of Recent Sciences ______________________________________________________________ ISSN 2277-2502Vol. 3(6), 96-104, June (2014) Res. J. Recent Sci. International Science Congress Association 100 this is shorter wire length and the minimum cost. The box center (x, y) is assigned through the smallest and the largest coordinate of x cells and calculation of y coordinate is carried out in the same way. This stage is a set of primary coordinates for TSV cells25 (figure 6). Figure-6 Primary Allocation of TSV After the initial configurations, the cells are separately placed in a row26. This is the method of configuration for TSV distribution row (the row which has distribution of the TSV cells). When the coordinates of TSV cells are specified and allocated, the connection between the signals in different layers can be corrected. The delay time of the circuit can be specified through a timed model, cells completion, and connections of TSV cells27. Queuing Area: Existent signals in different layers are verified by the TSV cell. When a TSV cell is specified, redistribution cost of the layer (RDL) can decrease. To guarantee satisfaction from the method, TSV cells in the layer of i (the top layer) should be placed along with landing cells in the layer of i-1 (the layer located lower than distribution of TSV cells). Following this method, more accurate connections can be created between small and landing pads28 (figure 7). Figure-7 TSV Queuing Area The coordinate of TSV cells should be specified for delay calculations. In order to prevent the problem of overlap between cells with TSV cells, movement is carried out in another way. A method is introduced into resolve the problem29. This method provides movement flow from the top layers to the bottom ones which can always do queuing area correctly. TSV cells in every layer will have no overlaps with any other cells30. As opposed to this, if TSV cells are specified, they will be observed from bottom layers to top layers because no TSV cell is available in the bottom layer and only landing cells will be specified. TSV cells in the top layer are applied to provide the row area and they can cause some problems to TSV cells and overlaps between cells in similar layers31. In order to collect these values, queuing area should be considered in 3D ICs. The main idea is also applied in this procedure. TSV cells are specified from the top layer to the bottom one so that no overlap between TSV cells and gained cells in the experimental results can be observed. Simulated Fusion-based Timed Movement: Simulated fusion is applied for progress and optimization of the timing in our timing movement. Simulate fusion algorithm is a kind of fusion process which is achieved through appropriate justification of cost functions in order to achieve appropriate performance. The cost of an inter-cell exchange is specified based on the connection edge. Decision for a cell exchange is made based on the exchange costs. If the total costs are positive, the cell starts Research Journal of Recent Sciences ______________________________________________________________ ISSN 2277-2502Vol. 3(6), 96-104, June (2014) Res. J. Recent Sci. International Science Congress Association 101 exchanging successfully. But if they are negative, it fails to exchange32. Allocated cells have small cracks which manage the most critical conditions. This criticality is described as follows: \r'G'43'G5'76H $AI%7*\nJ%0%A$ %0KL$0MN9 $K (10) Here ),,()(,(delaySlackrequiredarrivalrequired - - = . Where: )(arrivalis the require time of cell j, )(arrival is the time of entering to cell i, and the delay ( j i , ) is a connection delay between cells i and j. Here we introduce the cost function in performing movement timing. The cost function only considers the wire length and the network timing. Wire length performance and timing optimization are our main purposes. We try to achieve a better timing performance without an increase in wire length. In this regard, we use sections of wire-cost (11) and time-cost (13) as our cost function32. ?'\r2OPGR=&#x-230;&#x.719;?DET90/9U (11) 'V2OPG'7612345'76\r'G'43'G5'76\nJ%0%A$ %0KWX.YZ90 (12) 'V2OPG'V2OPG'7)%7*+[\""6\n (13) ]^]'V2OPG&#x-214;&#x.789;\r2_'O`P'V2OPG H^]a%9WJZ/0L9&%Z;/a%9WJZ/0 (14) Generalization: After total locating, there will still be overlaps between standard cells and TSV cells. We apply a special algorithm on the generalized algorithm of Tetris. Our method is similar to Tetris method along with a few modifications where the modifications make it possible for it to be used in 3D ICs. TSV cells are first generalized then standard cells will be. Generalizing TSV: There may be some overlaps between TSV cells in a row. In average cell distribution for a row, only modification and calculation x coordinate are taken into account. Coordinate of y in TSV cell was specified during the primary movement. Only distributed TSV cells in a row are considered in distribution. First, all TSV cells in a row are considered and new coordinate of x is calculated in which is in fact located in the box center. The reason for this is that the coordinates of the cells may change after locating in order to enhance the performance; therefore, this box is not in a similar network with a primary allocation status. Second, their classification is based on their x coordinates. If the TSV cell still continues overlapping other TSV cells after re-modifying its coordinate, its precise calculation of x coordinate will be carried out. The exact coordinate of x in is calculated after computing its costs33. An appropriate coordinate should include the minimum cost. Its method is as follows: Cell Generalization: After generalizing the TSV cell, we cope with the existent barrier on the way of these cells. The only thing that is required is management of the overlaps between the cells. Similar generalization has Tetris status. If the row width is not enough, the nearest row with similar direction will be found and then adjusted34. Experimental Results This algorithm has been compiled using C++. A computer with adual-coreprocessor,3GHzcache,and4096MB of RA Min Linux has been used. In the present study, our basic criteria are ISCAS85downloaded from35. The circuit has been explained in LEF/DEF format and the internal delays create standard delay files in sdf format. We modify 2D integral circuits in designing 3D ICs. This area reduces into nl where nl stands for the number of the layers. The pad situation has changed a little. After classifying the circuit, we create a locating circuit that has the largest area in these three layers. The area of the layer contains TSV cells. All of the inputs and outputs are located in the lower layer. The area of the TSV IO is 85 square micrometers. This figure is 255 square micrometers for the TSV cell. The ration of standard side cell in this area is 1.13:1. Table 1 presents the basic standard characteristics. Table 4 also presents the results of three-layer locating36,37. Research Journal of Recent Sciences ______________________________________________________________ ISSN 2277-2502Vol. 3(6), 96-104, June (2014) Res. J. Recent Sci. International Science Congress Association 102 Figure 4 shows the related technology along with the locating results c1908, TSV cells and their distribution, a red line which means the locating area, average blue blocks that mean TSV sections, green blocks which show TSV cells, and blue blocks that present the cells. TSV status on the layer of i-1 is allocated to TSV cell on the layer of i. Table-1 Basic Standard Characteristics ISCAS85 after Classifying the 3D IC Cell Number TSV Section Number TSV Cell Number Input File 880 105 105 c1908 1269 403 403 c2670 1669 139 139 c3540 2307 330 330 c5315 3513 531 531 c7552 Table-2 2D Movement after Generalization WNS (ps)TNS Critical Route HPWL Circuit -0.002 28 46970.87 73552.27 c1908 -0.002 28 38142.38 132360.72 c2670 -0.002 28 55242.35 197642.19 c3540 -0.004 28 57428.66 249188.64 c5315 -0.004 28 50797.82 480862.28 c7552 Table-3 3D Locating after Generalization and Specifying the Area WNS (ps) TNS Critical Route HPWL Circuit -0.006 28 46923.97 39964.83 c1908 0 0 38083.8 97814.48 c2670 0 0 54902.31 110990.16 c3540 -0.004 28 57177.56 181797.53 c5315 0.002 28 50379.83 286605.88 c7552 Table-4 Locating after Generalization and Specifying the Area WNS (ps) TNS Critical Route HPWL Circuit -0.004 28 46891.95 32086.79 c1908 -0.001 14 37821.84 72576.26 c2670 0 0 54861.85 78743.85 c3540 -0.0007 7 57208.76 161172.89 c5315 -0.002 228 50315.58 205572.98 ConclusionIn the present study, we have presented an alternative 3D procedure containing timing analysis. TSV cells were created through algorithms of classification-based locating. Allocating TSV cells always pushes aside adaptation barriers37. Is shown at figure 8 and table 5. Table-5 3D ICs Locating Progress Compared to 2D ICs Critical Route (PS) HPWLLayer Number Circuit 0.1% 44.66% 3 c1908 0.16% 53.38% 4 c1908 0.14% 24.1% 3 c2670 0.87% 46.17% 4 c2670 0.63% 41.81% 3 c3540 0.66% 59.13% 4 c3540 0.47% 26.12% 3 c5315 0.34% 33.32% 4 c5315 0.81% 39.9% 3 c7552 0.94% 56.24% 4 c7552 (a) (b) (c) Figure-8 TSV based Movement in Three-layer Section: (a) The Lower Layer, (b) The Middle Layer, (c) The Top Layer In this paper, a thermal control mechanism with an in-situ temperature sensor for TSV 3D-ICs is presented using thermal guard rings and thermal TSVs. Depending on the thermal guard ring and thermal TSVs, an analytical model for on-chip heat dissipation in each power-thermal domain is also presented in this paper. Based on the analytical model, the offset temperatures between the hotspots in the power-thermal domain and thermal guard ring can be calculated. Therefore, the in-situ temperature sensor is placed near the thermal guard ring to detect the temperature and feedback the thermal information for the system. The simulation results show the thermal control mechanism with an in-situ temperature sensor can reduce temperature and detect heat dissipation of TSV 3D-Ics significantly. The proposed thermal control mechanism can further achieve about 25.10% temperature reduction. This technique can be extended to balance workloads in the overall system for further reducing temperature. In the future, the most Research Journal of Recent Sciences ______________________________________________________________ ISSN 2277-2502Vol. 3(6), 96-104, June (2014) Res. J. Recent Sci. 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