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Clock Mesh Synthesis with Blockage Placement for Stub and Mesh Wire Minimisation

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Author Affiliations

  • 1VLSI Design, SRM University, Chennai, Tamil Nadu, INDIA
  • 2 Electronics and Communication Dept.,SRM University, Chennai,Tamil Nadu, INDIA

Res. J. Recent Sci., Volume 3, Issue (7), Pages 39-43, July,2 (2014)

Abstract

A method for optimizing clock mesh is proposed which diminishes the power in network significantly while considering timing slack. The proposed paper implements the methodology by introducing placement blockages during the IC design flow. Stub wire minimization is achieved by using register placement. Placement of blockages in order to further reduce the power dissipation along with optimized power density and guaranteed non negative timing slack is the main essence of the paper. The advantages of the proposed method when implemented over ISCAS’89 benchmark circuits are reduced power dissipation—26% on an average when analogized to previous works and significant reduction in wire length by 50% when compared to earlier uniform mesh works. Further, reduction of timing slack (1.2% of the clock period) provides added benefit.

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