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An Overview of through-Silicon via - based Three Dimensional integrated Circuits (3D IC) to placement to Optimize timing

Author Affiliations

  • 1Young Research Club, Sardasht Branch, Sardasht Islamic Azad University, Sardasht, IRAN

Res. J. Recent Sci., Volume 3, Issue (6), Pages 96-104, June,2 (2014)


Semiconductor technology continues its progress in the field of 3DICs. Using stack structures through silicon via (TSV), the concept of 3D IC deals with introducing another dimension in recent designs. In fact, 3D ICs accompanying with TSV cells replace the existent connections in 2D ICs. Optimizing 3D ICs; however, is still in its early stages in many aspects. There are still some problems in locating standard and TSV cells regarding time optimization. In the present study, after queuing the layer and based on its segmentation, first we proposed a methodology for locating cells. Then, we dealt with simultaneous addressing of the pressure caused by the queuing process. Simulated fusion was applied to optimize timing and reduce wire length. Finally, an appropriate method is used to prove the procedures so that it can omit the overlaps between the cells and also the TSV cells. The results of the conducted experiments showed that both wavelength and delay in critical routes are more important in 3D ICs compared to 2D ICs.


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